1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems using cache memory that incorporates at least one status bit associated with each data word within the cache memory.
2. Description of the Prior Art
It is known to provide cache memories, such as that illustrated in FIG. 1 of the accompanying drawings, that include store 2 containing address TAGs for lines of data in a cache RAM memory 4. The cache RAM memory 4 is composed of a plurality of cache lines 6, each cache line 6 storing four data words. A plurality of valid and dirty bits 8 are associated with each cache line 6. Common types of status bits 8 are a valid bit 10 and a dirty bit 12. The valid bit 10 indicates whether that cache line is storing valid data, e.g. at startup each cache line 6 must be marked as storing invalid data. The dirty bit 12 indicates in the context of a write back cache architecture that at least one data word with that cache line 6 has been changed since it was read from the main memory and accordingly needs writing back to the main memory when that cache line 6 is flushed from or replaced within the cache. It will be seen that as a compromise between circuit area and the degree of fine control that can be achieved with the status bits 8, each cache line 6 has one valid bit 10 associated with it and one dirty bit 12 associated with it (this is the arrangement used in the majority of cache implementations). Thus, the four data words within a cache line 6 share these status bits 8.
In certain operational situations it is desirable to make global changes to the status bits 8 of all of the cache lines 6 of a cache system. As an example, upon system startup, following an MMU change or following a context switch, it is often necessary to flush the entire contents of the cache by marking all of the valid bits 10 of each cache line 6 as invalid. One way of doing this is to sequentially access each of the valid bits 10 and write it invalid. In a cache system that may contain thousands of cache lines 6, this operation can take thousands of processing cycles and significantly impact system performance. An alternative to sequentially and individually altering each of the status bits 8 is to apply a global change through special purpose hardware that is able to change the status bits in parallel. Whilst this can provide fast operation, it has the disadvantage of consuming circuit area for this special purpose hardware and typically requires to be custom designed for each implementation of a more generic system design.